TM 11-7025-221-20
1-16. Multiplexer Section Block Diagram Discussion (V3/V4 Models) - Continued.
and compared by the microprocessor to a stored value. Any errors in this measurement result
in alarm displays.
The receiver on group modem card A20 processes the group modem conditioned diphase input.
A combined digital orderwire may also be received on this input. The group data and orderwire
inputs are separated and converted into TTL formats. Timing is recovered from the data. Group
data and timing are applied to the respective input buffer. Orderwire data are routed to 16 DVOW
card A7.
There are eight input buffers; one for each potential input port. Buffers for groups 1 and 2 are
located on mux card A6, Buffers for groups 3 through 8 are on mux input buffer card A5. Each
buffer provides an elastic storage function for one group input. Data for each group are clocked
into its buffer at its incoming data rate. Data are strobed out of the buffers and onto the mux
transmit data bus in response to mux strobes. Thus, data are clocked into each buffer at a regular
rate and strobed out when it is to be inserted into the SG.
Incoming 16 kb/s orderwire data from the KY-57/58 Vinson are processed by the Vinson buffer
on SSV card A2 for application to 16 DVOW card A7. Processing entails converting the data to
a TTL format and buffeting. The KY-57/58 Vinson is not synchronized to the TD-1337(V)/G. Therefore,
buffering is required to accommodate for differences between the clock source in the KY-57/58
Vinson and TD-1337(V)/G timing.
16 DVOW card A7 provides access to the mux transmit data bus for the 16 kb/s orderwires. The
three 16 kb/s orderwires are: the Vinson orderwire input from SSV card A2, the CNCE orderwire
input from group modem card A20, and the H-250 handset input. Only one input can be accepted
at a time, and entry is on a first-come, first-sewed basis. The H-250 handset input is in analog
form and is converted to a TTL format by 16 DVOW card A7, Data for a given orderwire are
processed and entered into a buffer. Data are strobed out and onto the mux transmit data bus
in response to mux strobes. Ring codes to be transmitted are received from the microprocessor
and strobed onto the mux transmit data bus.
Orderwire transmit circuits on 2.4 DVOW card A8 provide access to the mux transmit data bus
for the 2.4 kb/s ANDVT input. The input is converted to a TTL format and entered into a buffer.
In turn, data are strobed out and onto the mux transmit data bus in response to mux strobes.
Ring codes to be transmitted are received from 16 DVOW card A7 and strobed onto the mux
transmit data bus.
The loop modem receiver on loop modem/rt mess card A4 processes the incoming 16 kb/s or
32 kb/s conditioned diphase dedicated user input. The input is converted to a TTL format and
entered into a buffer. Data are strobed out and onto the mux transmit data bus in response to
mux strobes.
Under microprocessor control, CESE collector card Al monitors up to 56 external status points.
The status points are scanned and a message is assembled that is applied to red CESE assembly
A25 which converts the message to a 150 b/s serial data stream for application to an external
DLED. The DLED encrypts the message and applies it back to card Al as a 2 kb/s serial data
stream. The input from the DLED is converted to a TTL format and entered into a buffer. Data
are strobed out and onto the mux transmit data bus in response to mux strobes.
The mux circuits on mux card A6 generate mux strobes that control strobing of data onto the
mux transmit data bus. In this way, all parts of the SG are assembled in the proper sequence
and at the proper time. Data on the mux transmit data bus are converted to an unbalanced NRZ
format and applied to the modem.
PLL card A22 produces the major timing signals used to control TD-1337(V)/G operation. These
timing signals are derived from a voltage-controlled crystal oscillator (VCXO) on the card, Method
of VCXO control is based on the timing source selection made during configuration. If CNCE or
external standard selection is made, the VCXO is controlled by a phase-locked loop that receives
timing from one of the group inputs. If master is selected, the VCXO is driven to its nominal
mid-range by the microprocessor. If slave is selected, the VCXO is controlled by the microprocessor
in response to control telemetry data received in an incoming SG.
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